1. Field of the Invention
The invention relates to analog-to-digital converters (ADC), and more particularly to gain error calibration of ADCs.
2. Description of the Related Art
An analog-to-digital converter converts an analog input signal to a digital output signal. Analog-to-digital converters are classified into several categories including flash ADCs, pipelined ADCs, and cyclic ADCs. Among the three ADC categories, a flash ADC has the shortest latency, because it has the simplest circuit structure. A flash ADC comprises multiple comparators directly comparing an analog input signal with multiple reference voltages to generate a digital output signal. When the required resolution of a digital output signal increases, a flash ADC must include a great number of comparators, increasing circuit complexity and chip area thereof. Thus, a flash ADC is only used when resolution of the digital output signal is low.
Compared with a flash ADC, a pipelined ADC and a cyclic ADC require fewer comparators and occupy less chip area to generate a high resolution digital output signal. FIG. 1 is a block diagram of a conventional pipelined ADC 100. The pipelined ADC 100 comprises a plurality of stages 101-10N connected in series, with each stage generating a few bits of the digital output signal Dout. In the series, a preceding stage generates a stage output value indicating more significant bits of the digital output signal Dout, subtracts the stage output value from its stage input signal to obtain a residual signal, and amplifies the residual signal to obtain a stage output signal. A subsequent stage then receives the stage output signal of the preceding stage as a stage input signal thereof, and in the similar way generates its stage output value indicating less significant bits of the digital output signal Dout. For example, the second stage 102 generates a stage output value do2 and a stage output signal R2 according to its stage input signal R1, which is the stage output signal of the first stage 101. The gain error correction module 120 then collects the stage output values do1˜doN of stages 101˜10N to generate the final digital output signal Dout. Because each stage only generates a few bits of the digital output signal Dout, the signal resolution of the stage output value is lower and each stage requires fewer comparators to operate.
FIG. 2 is a block diagram of the first stage 101 of the pipelined ADC 100 of FIG. 1. The first stage 101 comprises a sample and hold module 202, a sub ADC 204, an adder 206, a sub DAC 208, a subtractor 210, and an amplifier 212. The sample and hold module 202 samples and holds a stage input signal Vin. Because the stage 101 is the first stage of the pipelined ADC 100, the stage input signal Vin is an analog input signal of the ADC 100. The sub ADC 204 then digitizes the stage input signal Vin to generate a stage output value do1 indicating the most important bits of the digital output signal Dout of the pipelined ADC 100. In one embodiment, the sub ADC 204 is a flash ADC.
The adder 206 then adds a correction number P1 to the stage output value do1 to obtain a sum value. The sub DAC 208 then converts the sum value from digital to analog to obtain a sum signal, and the subtractor 210 subtracts the sum signal from the stage input signal Vin to obtain a residual signal. The amplifier 212 then amplifies the residual signal according to a gain value G to generate the stage output signal R1. The stage output signal R1 is then received by a subsequent stage 102 as the stage input signal thereof, and the subsequent stages 102 similarly generate the stage output value do2 thereof. The other stages of the pipelined ADC 100 have a structure similar to that of the first stage 101 except for omission of the sample and hold module 202 and the adder 206. In other stages without an adder 206, a subtractor 210 directly subtracts a stage output value converted by a sub DAC 208 from the stage input signal to generate a residual signal, which is then amplified by an amplifier 212 to generate a stage output signal.
Before a stage delivers the residual signal to a subsequent stage, the residual signal is amplified according to a gain value, thus, the subsequent stage can more precisely generate a stage output value. Although an ideal gain value of a stage is predetermined to be a constant, a practical gain value of a stage often changes due to chip fabrication errors or chip temperature. The difference between the practical gain value and the ideal gain value is referred to as a gain error. Because the gain error of a current stage affects the stage output values of subsequent stages, the gain error must be calibrated when the final digital output signal Dout is generated according the stage output values do1˜doN. Thus, the gain error correction module 120 of FIG. 1 must estimate the gain error of some of the stages to improve precision of the digital output signal Dout.
To estimate the gain error of the first stage 101 of FIG. 1, the gain error correction module 120 generates a correction number P1 and delivers the correction number P1 to the first stage 101. The first stage 101 then processes the residual signal thereof according to the correction number P1 before it is amplified by the amplifier 212, as shown in FIG. 2. Thus, the stage output signal R1 of the first stage 101 is affected by the gain value of the amplifier 212 and values of the correction number P1. Because the stage input signals R1˜RN−1 of the subsequent stages 102˜10N are derived from the stage output signal R1 of the first stage 101, the stage output values do2˜doN of the subsequent stages 102˜10N are affected by values of the correction number P1. The gain error correction module 120 then correlates the stage output values do2˜doN of the subsequent stages 102˜10N with the correction number P1 to estimate an error of the gain value of the amplifier 212 of the first stage 101.
The gain error correction module 120 must collect a great number of samples of the stage output values do2˜doN to estimate the gain error of the first stage 101. The precision of the gain error estimate increases with the number of collected samples. If the number of collected samples is reduced, a low precision gain error estimate results, reducing the precision of the final digital output value Dout, thus degrading performance of the ADC 100. If the number of the collected samples is increased, the time required by collecting samples causes latency in signal conversion. Thus, a method for reducing time required for estimating gain errors of an ADC without reducing precision of a digital output signal is desirable.